FIG. 1 illustrates a pair of cells of an EEPROM according to the prior art. Cell 1 is composed of a selection transistor SG1 and a floating-gate transistor CG1. Transistor SG1 is intended to selectively block access to transistor CG1. Transistor CG1 is intended for the storage and reading of data. A second cell is composed of transistors SG2 and CG2 in a similar manner.
FIG. 2 illustrates such cells located in a memory plane 5. This memory plane accommodates two lines of two 2-bit words. Each column of the memory plane has one line CG<i> coupled to a column decoder. The signal from line CG<i> is selectively reproduced on the gates of the floating-gate transistors of a word line by means of an associate transistor SW. Each SW transistor is rendered conducting through the activation of a word line WL, coupled to a word-line decoder. The DL<i> lines are coupled to a data-line decoder.
These decoders are subject to various types of malfunction as they leave the production line.
For an address supplied to a decoder, the latter is able to activate two lines or columns simultaneously. No line or column can activate an unwanted line or column. Tests are thus conducted at the end of the production process in order to detect the memories that have defective decoders.
To test the operation of these decoders, different types of tests are already known. In particular, it is common to use an ATE tester external to the EEPROM, to design the memory with a view to its DFT testability, or to use self-test circuits incorporated into the memory BIST. Examples of such tests include the diagonal test or the test known as the “Checkerboard test”.
For the test of the diagonal, the technique includes programming the data words of the diagonal of the memory plane, and then reading the content of these words in order to determine if the addressing is correct. Since the programming can be affected only line by line, the testing time is significant, and involves a non-negligible additional memory production cost. As an example, for a 32 kB EEPROM with 512 lines, the programming time will typically be one second, and then the reading time will be 250 ms.
Manufacturers conventionally determine the cost of testing time in terms of silicon area. For example, for a memory in 0.18 μm technology, one second of test is equivalent to 0.02 mm2. Test circuits intended to reduce the testing time must therefore not occupy an area greater than the area equivalent to the time that they save.
Document WO03-003379 describes an EEPROM equipped with self-test circuits, intended to eliminate the programming stage of the test phase. To this end, additional cells are coupled to the word lines. These additional cells apply predetermined address data in the place of the cells of the memory plane, in order to avoid line-by-line programming of the cells of the memory plane. In this document, the additional cells are EEPROM memory cells transformed into ROM by the elimination or not of their bit-line contact.
Such an EEPROM nevertheless has drawbacks. In fact, the additional cells still occupy a non-negligible area of the substrate, which increases the cost of the EEPROM.